A semiconductor memory cell array typically includes a plurality of memory cells that are arranged in rows and columns. Moreover, such a memory cell array includes a plurality of bitlines and a plurality of wordlines. For example, the gate electrodes of rows of memory cell transistors are connected by wordlines, by which the memory cells are to be addressed.
An example of a non-volatile memory device is based on NROM technology. For example, a cross-sectional view is shown in FIG. 3 of an NROM cell between V and V as is shown in FIG. 1. In particular, the NROM cell is an n-channel MOSFET device, wherein the gate dielectric is replaced with a storage layer stack 27. As is shown in FIG. 3, the storage layer stack 27 is disposed above the channel 25 and under the gate electrode 26. The storage layer stack 27 includes a silicon nitride layer 272 which stores the charge and two insulating silicon dioxide layers 271, 273 which sandwich the silicon nitride layer 272. The silicon dioxide layers 271, 273 have a thickness larger than 2 nm to avoid any direct tunnelling. In the NROM cell shown in FIG. 3, two charges 221, 222 are stored at each of the edges adjacent to the n-doped source/drain regions 23, 24.
In a memory cell array with a plurality of memory cells of the manner shown in FIG. 3, the bitlines are implemented as doped portions 23, 24 and thus form buried bitlines 3. In other words, segments of the bitlines form the first and second source/drain regions 23, 24 of a corresponding memory cell. Moreover, segments of the wordlines form the gate electrode 26 of a corresponding memory cell. The NROM cell is programmed by channel hot electron injection (CHE), for example, whereas erasing is accomplished by hot hole enhanced tunnelling (HHET) by applying appropriate voltages to the corresponding bitlines and wordlines, respectively. Due to the charge trapped in the charge storage layer, the threshold voltage of the transistor is changed. By applying appropriate voltages to the corresponding wordlines and bitlines the changed threshold voltage and, thus, the stored information is detected.
Since, as has been described above, the bitlines are implemented as n-doped substrate portions, the problem arises that the resistance of the bitlines is comparatively high. Accordingly, usually metal bitlines (not shown in FIG. 3) are provided, the metal bitlines being arranged in a higher metallization layer above the semiconductor substrate 1 and gate electrodes 26. Each single bitline is connected with the supporting metal bitline at predetermined intervals by a bitline contact.
FIG. 1 shows a plan view of a memory cell array including a plurality of NROM cells as have been described with reference to FIG. 3. As can be seen, a plurality of wordlines 4 are provided. Moreover, a plurality of metal bitlines 5 are provided on top of the wordlines 4. The metal bitlines 5 are disposed directly above the buried bitlines (not shown in this drawing) which have been described above. FIG. 1 also shows a wordline removal portion 41 in which selected wordlines are removed. In the wordline removal portion 41, bitline contacts between the supporting bitlines 5 and the buried bitlines are provided. At a point of intersection between the wordlines 4 and the bitlines, memory cells 20 are provided. FIG. 1 shows a selected memory cell 21. For addressing the selected memory cell 21, it is necessary to address the two adjacent supporting bitlines 55, 56 as well as the corresponding wordline 42. As can be seen in FIG. 1, the supporting bitlines 5 are disposed directly above the buried bitlines and, consequently, have the same pitch.
FIG. 2 shows a cross-sectional view of a memory cell array, which is taken between I and I as can be taken from FIG. 1. As can be seen, buried bitlines 3 which are made of n-doped substrate portions are disposed adjacent to the surface 10 of a semiconductor substrate 1. In the wordline removal region 41 a plurality of bitline contacts 51 are provided. The bitline contacts 51 are made of a conductive material. Adjacent bitline contacts 51 are insulated from each other by the dielectric material 52. On top of the dielectric material 52 a plurality of supporting bitlines 5 are provided. The distance between neighbouring supporting bitlines 5 is denoted as Mp. Mp refers to the pitch of the array of supporting lines 5. In other words, Mp denotes the distance between the center of each of the supporting lines 5, respectively. Moreover, the buried bitlines 3 are arranged at a pitch Bp, wherein the pitch Bp can be measured from center to center of each of the buried bitlines or from the right or left edge to the right or left edge of each of the buried bitlines 3, respectively. As can be seen from FIG. 2, the pitch Bp of the buried bitlines 3 is equal to the pitch Mp of the supporting bitlines 5.